1. Technical Field
The present invention relates to a system and method for testing bus transaction and other processor unit logic on a multi-processor design. More particularly, the present invention relates to a system and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation.
2. Description of the Related Art
A processor test team typically employs test patterns to verify and validate a system design. Processor testing tools exist whose goal is to generate the most stressful test pattern for a processor. In theory, the generated test pattern should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test patterns.
Verifying and validating a processor using test patterns typically includes three stages, which are 1) test pattern build stage, 2) test pattern execution stage, and 3) validation and verification stage. A challenge found is that the test pattern build stage is typically the most time consuming process in any verification technique, which results in little time for test pattern execution and validation/verification.
In a multi-processor system, the processors typically share a front-side bus in which memory transactions travel. During these memory transactions, a bus arbitrator manages bus ownership at any given moment, which results in bus contention. A challenge found is that existing art executes many different test patterns to stress the bus differently, which requires a significant amount of test pattern generation time. Another challenge found is utilizing a set of test patterns in order to quickly maximize test pattern coverage.
What is needed, therefore, is a system and method for efficiently testing bus arbitration logic on a multi-processor system.